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19-1899; Rev 1; 5/04
12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference
General Description
The MAX1422 3.3V, 12-bit analog-to-digital converter (ADC) features a fully differential input, pipelined, 12stage ADC architecture with wideband track-and-hold (T/H) and digital error correction incorporating a fully-differential signal path. The MAX1422 is optimized for lowpower, high dynamic performance applications in imaging and digital communications. The converter operates from a single 3.3V supply, consuming only 137mW while delivering a 67dB (typ) signal-to-noise ratio (SNR) at a 5MHz input frequency and a 20Msps sampling frequency. The fully-differential input stage has a small signal -3dB bandwidth of 400MHz and may be operated with single-ended inputs. An internal 2.048V precision bandgap reference sets the ADCs full-scale range. A flexible reference structure accommodates an internally or externally applied buffered or unbuffered reference for applications requiring increased accuracy or a different input voltage range. In addition to low operating power, the MAX1422 features two power-down modes, a reference power-down, and a shutdown mode. In reference power-down, the internal bandgap reference is deactivated, resulting in a 2mA (typ) supply current reduction. For idle periods, a full shutdown mode is available to maximize power savings. The MAX1422 provides parallel, offset binary, CMOScompatible three-state outputs. The MAX1422 is available in a 7mm 7mm 1.4mm, 48-pin TQFP package and is specified over the commercial (0C to +70C) and extended industrial (-40C to +85C) temperature ranges. Pin-compatible higher-speed versions of the MAX1422 are also available. Please refer to the MAX1421 data sheet for 40Msps and the MAX1420 data sheet for 60Msps. Single 3.3V Power Supply 67dB SNR at fIN = 5MHz Internal 2.048V Precision Bandgap Reference Differential Wideband Input T/H Amplifier Power-Down Modes 130mW (Reference Shutdown Mode) 10W (Shutdown Mode) Space-Saving 48-Pin TQFP Package
Features
MAX1422
Ordering Information
PART MAX1422CCM MAX1422ECM TEMP RANGE 0C to +70C -40C to +85C PIN-PACKAGE 48 TQFP 48 TQFP
Pin Configuration
AGND AVDD CML REFN REFP REFIN AVDD AGND PD OE D11 D10
48 47 46 45 44 43 42 41 40 39 38 37
________________________Applications
Medical Ultrasound Imaging CCD Pixel Processing Data Acquisition Radar IF and Baseband Digitization
AGND AVDD AVDD AGND AGND INP INN AGND AGND AVDD AVDD AGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
D9 D8 D7 D6 DVDD DVDD DGND DGND D5 D4 D3 D2
MAX1422
Functional Diagram appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
AGND AVDD AVDD AGND CLK CLK AGND AVDD DVDD DGND D0 D1
TQFP
1
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12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422
ABSOLUTE MAXIMUM RATINGS
AVDD, DVDD to AGND ..............................................-0.3V to +4V DVDD, AVDD to DGND..............................................-0.3V to +4V DGND to AGND.....................................................-0.3V to +0.3V INP, INN, REFP, REFN, REFIN, CML,CLK, CLK, ....................(AGND - 0.3V) to (AVDD + 0.3V) D0-D11, OE, PD .......................(DGND - 0.3V) to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin TQFP (derate 21.7mW/C above +70C)........1739mW Operating Temperature Ranges MAX1422CCM ....................................................0C to +70C MAX1422ECM .................................................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage at -0.5dBFS, internal reference, fCLK = 20MHz (50% duty cycle); digital output load CL = 10pF, +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Differential Nonlinearity Integral Nonlinearity Mid-scale Offset Mid-scale Offset Temperature Coefficient RES DNL INL MSO MSOTC Internal reference (Note 1) Gain Error GE External reference applied to REFIN, (Note 2) External reference applied to REFP, CML, and REFN (Note 3) Gain Error Temperature Coefficient Signal-to-Noise Ratio Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-Noise and Distortion Effective Number of Bits Two-Tone Intermodulation Distortion Differential Gain Differential Phase ANALOG INPUTS (INP, INN, CML) Input Resistance Input Capacitance Common-Mode Input Level (Note 5) RIN CIN VCML Either input to ground Either input to ground 61 4 VAVDD 0.5 k pF V GETC External reference applied to REFP, CML, and REFN (Note 3) fIN = 5MHz, TA = +25C fIN = 5MHz, TA = +25C fIN = 5MHz, TA = +25C fIN = 5MHz, TA = +25C fIN = 5MHz fIN1 = 7.028MHz, fIN2 = 8.093MHz (Note 4) 60 63 64 -5 -5 -1.5 15 10-6 TA = +25C, no missing codes TA = TMIN to TMAX TA = TMIN to TMAX -3 -1 0.5 2 .75 3 10-4 0.1 0.2 5 5 1.5 %/C %FSR 3 12 1 Bits LSB LSB %FSR %/C SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (fCLK = 20MHz, 4096-point FFT) SNR SFDR THD SINAD ENOB IMD DG DP 67 74 -72 65 10.5 -77 1 0.25 -63 dB dBc dBc dB Bits dBc % Degrees
2
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12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage at -0.5dBFS, internal reference, fCLK = 20MHz (50% duty cycle); digital output load CL = 10pF, +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Common-Mode Input Voltage Range (Note 5) Differential Input Range Small-Signal Bandwidth Large-Signal Bandwidth Overvoltage Recovery SYMBOL VCMVR VIN BW-3dB FPBW -3dB OVR VINP - VINN (Note 6) (Note 7) (Note 7) 1.5 FS input CONDITIONS MIN TYP VCML 5% VDIFF 400 150 1 MAX UNITS V V MHz MHz Clock cycles
MAX1422
INTERNAL REFERENCE (REFIN bypassed with 0.22F in parallel with 1nF) Common-Mode Reference Voltage Positive Reference Voltage Negative Reference Voltage Differential Reference Voltage VCML VREFP VREFN VDIFF At CML At REFP At REFN (Note 6) VAVDD 0.5 VCML + 0.512 VCML - 0.512 1.024 5% 100 V V V V ppm/C
Differential Reference REFTC Temperature Coefficient EXTERNAL REFERENCE (VREFIN = 2.048V) REFIN Input Resistance REFIN Input Capacitance REFIN Reference Input Voltage Range Differential Reference Voltage Range REFP, REFN, CML Input Current REFP, REFN, CML Input Capacitance Differential Reference Voltage Range CML Input Voltage Range REFP Input Voltage Range REFN Input Voltage Range RIN CIN VREFIN VDIFF (Note 6) (Note 8) 5
k 10 2.048 10% pF V V
0.92 1.08 VREFIN/2 VREFIN/2 VREFIN/2 -200 15 200
EXTERNAL REFERENCE (VREFIN = 0, reference voltage applied to REFP, REFN, and CML) IIN CIN VDIFF VCML VREFP VREFN (Note 6) A pF V V V V
1.024 10% 1.65 10% VCML + VDIFF/2 VCML VDIFF/2 0.7 VDVDD 0.3 VDVD
DIGITAL INPUTS (CLK, CLK, PD, OE) Input Logic High Input Logic Low VIH VIL V V
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3
12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage at -0.5dBFS, internal reference, fCLK = 20MHz (50% duty cycle); digital output load CL = 10pF, +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Input Current Input Capacitance DIGITAL OUTPUTS (D0-D11) Output Logic High Output Logic Low Three-State Leakage Three-State Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage Analog Supply Current Analog Supply Current with Internal Reference in Shutdown Analog Shutdown Current Digital Supply Current Digital Shutdown Current Power Dissipation Power-Supply Rejection Ratio TIMING CHARACTERISTICS Maximum Clock Frequency Clock High Clock Low Pipeline Delay (Latency) Aperture Delay Aperture Jitter Data Output Delay Bus Enable Time Bus Disable Time tAD tAJ tOD tBE tBD fCLK tCH tCL Figure 6 Figure 6, clock period 50ns Figure 6, clock period 50ns Figure 6 Figure 10 Figure 10 Figure 6 Figure 5 Figure 5 5 20 25 25 7 2 2 10 5 5 14 MHz ns ns Clock cycles ns ps ns ns ns PDISS PSRR IDVDD PD = DVDD Analog power dissipation (Note 9) 137 1 VAVDD VDVDD IAVDD VREFIN = 0 PD = DVDD 3 20 152 3.138 2.7 3.3 3.3 39 37 3.465 3.63 46 44 20 V V mA mA A mA A mW mV/V VOH VOL IOH = 200A IOL = -200A VDVDD - 0.5 0 -10 2 VDVDD 0.5 10 V V A pF SYMBOL CLK, CLK PD OE -20 -20 10 CONDITIONS MIN TYP 330 20 20 pF A MAX UNITS
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: 4
Internal reference, REFIN bypassed to AGND with a combination of 0.22F in parallel with 1nF capacitor. External 2.048V reference applied to REFIN. Internal reference disabled. VREFIN = 0, VREFP = 2.162V, VCML = 1.65V, and VREFN = 1.138V. IMD is measured with respect to either of the fundamental tones. Specifies the common-mode range of the differential input signal supplied to the MAX1422. VDIFF = VREFP - VREFN. Input bandwidth is measured at a 3dB level. VREFIN is internally biased to 2.048V through a 10k resistor. Measured as the ratio of the change in mid-scale offset voltage for a 5% change in VAVDD, using the internal reference.
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12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422
Typical Operating Characteristics
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = 1.024V, differential input drive, AIN = -0.5dBFS, fCLK = 20MHz (50% duty cycle) digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25 C.)
FFT PLOT (4096-POINT DATA RECORD)
MAX1422 toc01
FFT PLOT (4096-POINT DATA RECORD)
MAX1422 toc02
FFT PLOT (4096-POINT DATA RECORD)
fIN = 19.8051MHz
MAX1422 toc03
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 0
fIN = 5.2235MHz
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120
fIN = 8.1637MHz
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120
HD2 HD3
HD3
HD2
HD2
HD3
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT (4096-POINT DATA RECORD)
MAX1422 toc04
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
MAX1422 toc05
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX1422 toc06
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 0
fIN1 = 7.0283MHz fIN2 = 8.0931MHz fCLK = 20.0056MHz AIN1 = AIN2 = -6.5dB FS fIN1 IMD2 IMD3
85
70
fIN2 SFDR (dBc)
77
66
61
SNR (dB) 1 10 ANALOG INPUT FREQUENCY (MHz) 100
69
62
58
53
54
45 1 2 3 4 5 6 7 8 9 10 ANALOG INPUT FREQUENCY (MHz)
50 1 10 ANALOG INPUT FREQUENCY (MHz) 100
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1422 toc07
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1422 toc08
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER (fIN = 5MHz)
70 60 SFDR (dBc) 50 40 30 20
MAX1422 toc09
-50
70
80
-56
66 SINAD (dB)
THD (dBc)
-62
62
-68
58
-74
54 10 0 1 10 ANALOG INPUT FREQUENCY (MHz) 100 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT POWER (dB FS)
-80 1 10 ANALOG INPUT FREQUENCY (MHz) 100
50
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5
12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = 1.024V, differential input drive, AIN = -0.5dBFS, fCLK = 20MHz (50% duty cycle) digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25 C.)
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER (fIN = 5MHz)
MAX1422 toc10
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER (fIN = 5MHz)
MAX1422 toc11
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER (fIN = 5MHz)
70 60 SINAD (dB) 50 40 30
MAX1422 toc12
100
-10 -20 -30 THD (dBc)
80
80
SNR (dB)
60
-40 -50 -60
40
20 -70 0 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT POWER (dB FS) -80 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT POWER (dB FS)
20 10 0 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT POWER (dB FS)
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE
fIN = 5.5224MHz
MAX1422 toc13
SIGNAL-TO-NOISE RATIO vs. TEMPERATURE
MAX1422 toc14
TOTAL HARMONIC DISTORTION vs. TEMPERATURE
fIN = 5.5224MHz -69
MAX1422 toc15
84
70 fIN = 5.5224MHz 68
-67
80 SFDR (dBc)
SNR (dB)
76
72
64
THD (dBc) -40 -15 10 35 60 85
66
-71
-73
68
62
-75
64 -40 -15 10 35 60 85 TEMPERATURE (C)
60 TEMPERATURE (C)
-77 -40 -15 10 35 60 85 TEMPERATURE (C)
SIGNAL-TO-NOISE PLUS DISTORTION vs. TEMPERATURE
fIN = 5.5224MHz 68 SINAD (dB)
MAX1422 toc16
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1422 toc17
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1422 toc18
70
2
0.50
1 DNL (LSB) 0 1024 2048 3072 4096 INL (LSB)
0.25
66
0
0
64 -1
62
-0.25
60 -40 -15 10 35 60 85 TEMPERATURE (C)
-2 DIGITAL OUTPUT CODE
-0.50 0 1024 2048 3072 4096 DIGITAL OUTPUT CODE
6
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12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = 1.024V, differential input drive, AIN = -0.5dBFS, fCLK = 20MHz (50% duty cycle) digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25 C.)
GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V)
MAX1422 toc19
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX1422 toc20
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
CL = 10pF 5 4 IDVDD (mA)
MAX1422 toc21
0.5 0.2 GAIN ERROR (%FSR)
50 46
6
IAVDD (mA)
-0.1
42
3 2
-0.4 -0.7
38
34 30 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
1 0 -40 -15 10 35 60 85 TEMPERATURE (C)
-1.0
SNR/SINAD, THD/SFDR vs. CLOCK FREQUENCY
75 SNR/SINAD, THD/SFDR (dB, dBc) 70 65 60 55 50 45 40 fIN = 5MHz 5.0 7.5 10.0 12.5 15.0 17.5 20.0 2.00 3.1 SINAD SNR SFDR THD VREFIN (V) 2.03
MAX1422 toc22
INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
MAX1422 toc23
80
2.05 2.04
2.02
2.01
3.2
3.3 VDD (V)
3.4
3.5
CLOCK FREQUENCY (MHz)
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1422 toc24
OUTPUT NOISE HISTOGRAM (DC-INPUT)
27360 25,000 20,000
MAX1422 toc25
2.10
30,000
2.08
VREFIN (V)
COUNTS
2.06
16623 15029 15,000 10,000
2.04 3431 2596 22 310 162 2 1 DIGITAL OUTPUT NOISE N-4 N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5
2.02
5000 0 -40 -15 10 35 60 85 TEMPERATURE (C)
2.00
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7
12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422
Pin Description
PIN 1, 4, 5, 8, 9, 12, 13, 16, 19, 41, 48 2, 3, 10, 11, 14, 15, 20, 42, 47 6 7 17 18 NAME AGND FUNCTION Analog Ground. Connect all return paths for analog signals to AGND. Analog Supply Voltage. For optimum performance, bypass to the closest AGND with a parallel combination of a 0.1F, and a 1nF capacitor. Connect a single 10F and 1F capacitor combination between AVDD and AGND. Positive Analog Signal Input Negative Analog Signal Input Clock Frequency Input. Clock frequency input ranges from 100kHz to 20MHz. Complementary Clock Frequency Input. This input is used for differential clock input. If the ADC is driven with a single-ended clock, bypass CLK with 0.1F capacitor to AGND. Digital Supply Voltage. For optimum performance, bypass to the closest DGND with a parallel combination of a 0.1F and a 1nF capacitor. Connect a single 10F and 1F capacitor combination between DVDD and DGND. Digital Ground Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB. Digital Data Outputs. D6 through D11, where D11 represents the MSB. Output Enable Input. A logic "1" on OE places the outputs D0-D11 into a high-impedance state. A logic "0" allows for the data bits to be read from the outputs. Shutdown Input. A logic "1" on PD places the ADC into shutdown mode. External Reference Input. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To disable the internal reference, connect REFIN to AGND. Positive Reference I/O. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF. With the internal reference disabled (REFIN = AGND), REFP should be biased toVCML + VDIFF/2. Negative Reference I/O. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF. With the internal reference disabled (REFIN = AGND), REFN should be biased to VCML - VDIFF/2. Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF. With the internal reference disabled (REFIN = AGND).
AVDD INP INN CLK CLK
21, 31, 32 22, 29, 30 23-28 33-38 39 40 43
DVDD DGND D0-D5 D6-D11 OE PD REFIN
44
REFP
45
REFN
46
CML
Detailed Description
The MAX1422 uses a 12-stage, fully differential, pipelined architecture (Figure 1), that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle. Including the delay through the output latch, the latency is seven clock cycles. A 2-bit (2-comparator) flash ADC converts the heldinput voltage into a digital code. The following digital-
to-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held-input signal. The resulting error signal is then multiplied by two and the product is passed along to the next pipeline stage. This process is repeated until the signal has been processed by all 12 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes.
8
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12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference
Input Track-and-Hold Transconductance Circuit
Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuit in both track-and-hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuit samples the input signal onto the two capacitors (C2a and C2b) through-switches (S4a and S4b). Switches S2a and S2b set the common mode for the transconductance amplifier (OTA) input and open simultaneously with S1, sampling the input waveform. The resulting differential voltage is held on capacitors C2a and C2b. Switches S4a and S4b, are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier, and switch S4c is closed. The OTA is used to charge capacitors, C1a and C1b, to the same values originally held on C2a and C2b. This value is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. The wide input bandwidth, T/H amplifier allows the MAX1422 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs INP and INN can be driven either differentially or single-ended. Match the impedance of INP and INN and set the common-mode voltage to midsupply (AV DD /2) for optimum performance.
Analog Input and Reference Configuration
The full-scale range of the MAX1422 is determined by the internally generated voltage difference between REFP (AVDD/2 + VREFIN/4) and REFN (AVDD/2 - VREFIN/4). The MAX1422's full-scale range is adjustable through REFIN, which provides a high input impedance for this purpose. REFP, CML (AVDD/2), and REFN are internally buffered, low impedance outputs. The MAX1422 provides three modes of reference operation: * Internal reference mode * Buffered external reference mode * Unbuffered external reference mode In internal reference mode, the on-chip 2.048V bandgap reference is active and REFIN, REFP, CML, and REFN, left floating. For stability purposes bypass REFIN, REFP, REFN, and CML with a capacitor network of 0.22F, in parallel with a 1nF capacitor to AGND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In unbuffered external reference mode, REFIN is connected to AGND, which deactivates the on-chip buffers of REFP, CML, and REFN. With their buffers shut down,
MAX1422
MDAC VIN T/H x2 VOUT TO NEXT STAGE DAC 2 BITS IN+ C2a S4c VIN S4a
INTERNAL BIAS S2a C1a
CML S5a S3a
FLASH ADC
OUT S1 OTA OUT S4b C2b C1b
STAGE 1
STAGE 2
STAGE 12
IN-
DIGITAL CORRECTION LOGIC 12 D11-D0 S2b INTERNAL BIAS S5b CML
S3b
Figure 1. Pipelined Architecture
Figure 2. Internal T/H Circuit
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9
12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422
AVDD 50 R 0.22F AVDD 2 R
MAX4284
CML 0.1nF
50 REFP R 0.22F 0.1nF
R AVDD 2 AVDD 4
MAX4284
MAX1422
R 50 REFN 0.22F AVDD 4 R REFIN R AGND 0.1nF R
1V
Figure 3. Unbuffered External Reference Drive--Internal Reference Disabled
these nodes become high impedance and can be driven by external reference sources, as shown in Figure 3.
Clock Inputs (CLK, CLK)
The MAX1422's CLK and CLK inputs accept both single-ended and differential input operation, and accept CMOS-compatible clock signals. If CLK is driven with a single-ended clock signal, bypass CLK with a 0.1F capacitor to AGND. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to have the lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the ADC according to the following relationship: 1 SNRdB = 20 x log10 2 x IN x t AJ where fIN represents the analog input frequency, and tAJ is the aperture jitter. Clock jitter is especially critical for high input frequency applications. The clock input should always be consid-
ered as an analog input and routed away from any analog or digital signal lines. The MAX1422 clock input operates with a voltage threshold set to AVDD/2. Clock inputs must meet the specifications for high and low periods, as stated in the Electrical Characteristics. Figure 4 shows a simplified model of the clock input circuit. This circuit consists of two 10k resistors to bias the common-mode level of each input. This circuit may be used to AC-couple the system clock signal to the MAX1422 clock input.
Output Enable (OE), Power-Down (PD) and Output Data (D0-D11)
With OE high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power-down. All data outputs, D0 (LSB) through D11 (MSB), are TTL/CMOS logic compatible. There is a seven clockcycle latency between any particular sample and its valid output data. The output coding is in offset binary format (Table 1). The capacitive load on the digital outputs D0 through D11 should be kept as low as possible (10pF) to avoid large digital currents that could feed back into the ana-
10
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12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422
INP ADC INN
tBE tBD HIGH-Z OE
D11-D0
AVDD
OUTPUT DATA D11-D0 HIGH-Z VALID DATA
10k CLK
10k
Figure 5. Output Enable Timing
10k CLK AGND 10k
MAX1422
Table 1. MAX1422 Output Code For Differential Inputs
DIFFERENTIAL INPUT VOLTAGE* VREF 2047/2048 VREF 2046/2048 VREF 1/2048 0 -VREF 1/2048 -VREF 2046/2048 DIFFERENTIAL INPUT +FULL SCALE 1LSB +FULL SCALE 2LSB +1 LSB Bipolar Zero -1 LSB -FULL SCALE +1 LSB OFFSET BINARY
Figure 4. Simplified Clock Input Circuit
log portion of the MAX1421, thereby degrading its dynamic performance. The use of digital buffers (e.g. 74LVCH16244) on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the MAX1422 dynamic performance, add small 100 series resistors to the digital output paths, close to the ADC. Figure 5 displays the timing relationship between output enable and data output.
1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
System Timing Requirements
Figure 6 depicts the relationship between the clock input, analog input, and data output. The MAX1422 samples the analog input signal on the rising edge of CLK (falling edge of CLK). and output data is valid seven clock cycles (latency) later. Figure 6 also displays the relationship between the input clock parameters and the valid output data.
-VREF -FULL SCALE 2047/2048 *VREF = VREFP - VREFN
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX1422 for optimum performance. Connecting the center tap of the transformer to CML provides an AVDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a 1:2 or 1:4 step-up transformer may be selected to reduce the drive requirements. In general, the MAX1422 provides better SFDR and THD with fully differential input signals over singleended input signals, especially for very high input frequencies. In differential input mode, even-order harmonics are suppressed and each of the inputs requires only half the signal swing compared to singleended mode.
Applications Information
Figure 7 depicts a typical application circuit containing a single-ended to differential converter. The internal reference provides an AVDD/2 output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter at the input suppresses some of the wideband noise associated with high-speed op amps. Select the R ISO and CIN values to optimize the filter performance and to suit a particular application. For the application in Figure 7, a RISO of 50 is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor.Connecting CIN from INN to INP may further improve dynamic performance.
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11
12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422
7 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 N+7
ANALOG INPUT
CLK CLK tDO N-8 N-7 N-6 N-5 tCH N-4 tCL N-3 N-2 N-1 N
DATA OUTPUT
Figure 6. System and Output Timing Diagram
Single-Ended, AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application, using a MAX4108 op amp. This configuration provides high-speed, high-bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces, and remove digital ground and power planes from underneath digital outputs. Keep all signal lines short and free of 90 degree turns.
Grounding, Bypassing and Board Layout
The MAX1422 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass REFP, REFN, REFIN, and CML with a parallel network of 0.22F capacitors and 1nF to AGND. AVDD should be bypassed with a similar network of a 10F bipolar capacitor in parallel with two ceramic capacitors of 1nF and 0.1F. Follow the same rules to bypass the digital supply DV DD to DGND. Multilayer boards with separate ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arrangement to match the physical location of the analog ground (AGND) and the digital output driver ground (DGND) on the ADCs package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. Alternatively, all ground pins could share the
Static Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight-line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1422 are measured using the best straight-line fit method. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes.
Dynamic Parameter Definitions
Aperture Jitter Figure 10 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
12
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12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422
5V
0.1F LOWPASS FILTER MAX4108 300 0.1F RISO 50 0.1F CIN* 22pF INP
-5V
600 300 600 44pF* CML 5V 0.1F 5V 0.1F INPUT 0.1F MAX4108 300 0.1F MAX4108 INN RISO 50 0.1F CIN* 22pF LOWPASS FILTER 600 0.22F 1nF
MAX1422
-5V
300 -5V
300 300 300 *TWO CIN (22pF) CAPS MAY BE REPLACED BY ONE 44pF CAP, TO IMPROVE PERFORMANCE.
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion
Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 10). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical, minimum analog-to-digital noise is caused by quantization error only and results directly from the ADCs resolution (N-Bits): SNR(MAX) = (6.02 N + 1.76)dB In reality, there are other noise sources besides quantization noise e.g., thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADCs error consists of quantization noise only. ENOB is computed from: ENOB = SINAD -1.76 6.02
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13
12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422
Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: THD = 20 x log 10 V2 2 + V3 2 + V4 2 + V5 2 V1 Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale.
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
25 22pF * 0.1F VIN 1 N.C. 2 3 T1 6 5 4 0.22F 1nF 44pF * MAX1422 CML INP
VIN MAX4108 100
0.1F
RISO 50 INP 1k CIN 22pF
MAX1422
CML 0.22F 1nF RISO 50 INN CIN 22pF
MINICIRCUITS T1-1T-KK81 25 22pF * INN
100
*REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN INP AND INN TO IMPROVE DYNAMIC PERFORMANCE.
Figure 9. Single-Ended AC-Coupled Input
Figure 8. Using a Transformer for AC-Coupling
Functional Diagram
CLK CLK CLK CLK INTERFACE ANALOG INPUT INP tAD tAJ SAMPLED DATA (T/H) PD HOLD T/H INN PIPELINE ADC OUTPUT DRIVERS D11-D0 AVDD AGND
MAX1422
BANDGAP REFERENCE
REF SYSTEM + BIAS
DVDD DGND
T/H
TRACK
TRACK REFIN REFP CML REFN OE
Figure 10. T/H Aperature Timing
14
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12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
32L/48L,TQFP.EPS
MAX1422
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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